1. Technical Field
The present invention relates generally to application specific integrated circuits, and more particularly, to a multiple supply gate-array backfill structure.
2. Related Art
Application specific integrated circuits (ASIC) are designed by preparing a schematic layout specification in which structures are interconnected to form particular logical functions. The actual preparation may include using automated design software that provides, for example, synthesis, placement and routing of circuitry. For standard logical functions, libraries of cell structures exist that provide the necessary cell structures, which can be selected to generate the particular functions desired. Examples of functions include inverters, ANDs, NORs, etc. The design software places the appropriate cell structures in the ideal positions on the layout and then routes the structures together. Despite advanced design software packages, however, it is often necessary to modify the original layout after manufacture to address logic design problems. Unfortunately, preparing a full mask set that accommodates design modifications is expensive and creates long turnaround times prior to getting the fixed parts.
In order to address the modification problem, a number of techniques exist that take advantage of spaces on the integrated circuit (IC) that are not used to implement functions. These unused spaces exist in practically all ICs. One technique to allow for modifications is to provide spare circuits in the original layout and mask set. The spare circuits are spread throughout the IC design in the unused spaces, and are selected to provide a representative mix of functions. This technique, however, does not guarantee that the appropriate circuit will be available in the correct location when a modification is required.
Another technique that addresses design changes is to provide partially defined structures referred to herein as ‘gate array backfill structures’ that are placed in the unused space within the original layout and mask set. A modification can then be made by reprogramming the gate array backfill structures to perform a logic function. In one example, the gate array backfill structures are modified by a metal only modification. Modifications made using this technique are less expensive because they require minimal additional mask levels, and are faster because a full wafer processing is not required because the diffused layers may be processed ahead of the change, which only impacts the metal layers. A library of circuits, all of which use the same backfill cell for the diffused layers, but implement different logical functions requiring only metal changes, can be used to implement these modifications. Some techniques for providing gate array backfill cell structures are discussed in U.S. Pat. Nos. 5,369,595, 5,051,917 and 4,786,613.
Referring to FIG. 1, a conventional gate array backfill structure 14 is shown. Structure 14 includes a continuous n-well 18 that is shared by a number of transistors 16 and other adjacent circuitry (not shown). A voltage terminal 22 supplies the circuit voltage. The illustrative backfill structure 14 of FIG. 1 may be provided in an IC using a single voltage. In this case, the backfill structure 14 is limited to using the predetermined voltage of the IC and cannot be reprogrammed to accommodate a second, different voltage. Voltage islands are partitioned areas within an IC, each having a particular voltage supply. Voltage islands have found increasing usage because they allow for customization of power supply to different parts of an IC, which reduces power consumption.
Where voltage islands are used on an IC, backfill structure 14 may also be provided amongst the voltage islands. The use of voltage islands, however, presents a variety of problems relative to the conventional modification techniques discussed above. In particular, while typical gate array backfill cell structures 14 are usable to correct problems within voltage islands, they are unusable where an interconnection physically crosses over a voltage island or crosses a voltage island boundary because of the voltage differences involved. For example, if a voltage island is provided in the middle of an IC and a signal having nothing to do with the voltage island must physically cross the voltage island, the signal may need to be buffered. Unfortunately, it is impossible to place a buffer circuit into a voltage island in most cases because the buffer circuit up-level is referenced to the wrong voltage, i.e., the voltage of the voltage island. Accordingly, if a modification requires, for example, an interconnection of voltage islands or a signal inversion across a voltage island, current modification technology is incapable of implementation.
In view of the foregoing, a need exists for a gate array backfill cell structure that does not have the problems of the related art.